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This ZIP File is associated with Rev 1 of the Application Note


    Title (EE-295: Implementing Delay Lines on SHARC Processors)  


that can be found at http://www.analog.com/ee-notes.


Date Created:	October 25th, 2006


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Example 1 "ADSP-21262 EZ-KIT LITE Block Based Delay line" illustrates the implementation
of Block based delay lines based as explained in EE-295.

Source Files contained in this directory:

Block Based Delay line.dpj      VisualDSP project file
init1835viaSPI.c    ADSP-21262 source - SPI Flash Subroutines
initDAI.c           Set up the DAI to connect to the AD1835
main.c              Main section to call setup routines
initSPORT.c         Initialize the SPORT DMA to communicate with the AD1835
IRQprocess.c        Set up and process IRQ1 and IRQ2 (Pushbutton) interrupts
SPORTisr.c          Process SPORT 0 interrupts
blockProcess.c      Process the audio data in the current block
ad1835.h            Macro Definitions for AD1835 registers
tt.h                Includes and external declarations used for all files
TransmitDMA.c       Parallel port set up to transmit block of data from external memory
writeDMA.c          Setup for delayline Write DMA
ReadDMA.c           Setup for delayline Read DMA
ReceiveDMA.c        Parallel port set up to receive block of data from external memory
Delayprocessing.c   Delay line processing of FIR filter.

Dependencies contained in VisualDSP++ default include path:
def21262.h               Header file with generic definitions


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All code examples have been written and tested with

	VisualDSP++ 4.5 September Update

	ADSP-21262 revision 0.0

	ADSP-21262 EZ-KIT Lite revision 1.1


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